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PRELIMINARY
MX29F1615
16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM FEATURES * * * * *
5V 10% write and erase JEDEC-standard EEPROM commands Endurance:100 cycles Fast access time: 90/100/120ns Auto Erase and Auto Program Algorithms - Automatically erases the whole chip - Automatically programs and verifies data at specified addresses Status Register feature for detection of program or erase cycle completion Low VCC write inhibit is equal to or less than 3.2V
* Software and hardware data protection * Page program operation
- Internal address and data latches for 64 words per page - Page programming time: 0.9ms typical Low power dissipation - 30mA typical active current - 1uA typical standby current CMOS and TTL compatible inputs and outputs Package Type: - 42 lead PDIP
* * *
* *
GENERAL DESCRIPTION
The MX29F1615 is a 16-mega bit Flash memory organized as either 1M wordx16 or 2M bytex8. MXIC's Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memory. The MX29F1615 is packaged in 42-pin PDIP. It is designed to be reprogrammed and in standard EPROM programmers. The standard MX29F1615 offers access times as fast as 90ns,allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29F1615 has separate chip enables(CE) and output enable (OE) control. MXIC's Flash memories augment EPROM functionality with electrical erasure and programming. The MX29F1615 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. To allow for simple in-system reprogrammability, the MX29F1615 requires high input voltages (10V) on BYTE/ VPP pin for programming. Reading data out of the device is similar to reading from an EPROM. MXIC Flash technology reliably stores memory contents even after 100 cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F1615 uses a 5V 10% VCC supply to perform the Auto Erase and Auto Program algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.
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PIN CONFIGURATIONS
42 PDIP(600mil)
A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE/VPP GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
PIN DESCRIPTION
SYMBOL A0 - A19 Q0 - Q14 Q15/A - 1 CE OE BYTE/VPP VCC GND PIN NAME Address Input Data Input/Output Q15(Word mode)/LSB addr.(Byte mode) Chip Enable Input Output Enable Input Word/Byte Selection Input/Write Enable Input Power Supply Ground Pin
MX29F1615
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BLOCK DIAGRAM
CE OE BYTE/VPP
CONTROL INPUT LOGIC
PROGRAM/ERASE HIGH VOLTAGE
WRITE STATE MACHINE (WSM)
COMMAND INTERFACE REGISTER
X-DECODER
MX29F1615 FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE
(CIR)
ADDRESS LATCH
Q15/A-1 A0-A19
AND BUFFER
COMMAND DATA DECODER
Y-DECODER
SENSE AMPLIFIER
PGM DATA HV
COMMAND DATA LATCH
PAGE PROGRAM DATA LATCH
Q0-Q15/A-1
I/O BUFFER
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Table1.PIN DESCRIPTIONS
SYMBOL A0 - A19 Q0 - Q7 TYPE INPUT INPUT/OUTPUT NAME AND FUNCTION ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle. LOW-BYTE DATA BUS: Input data and commands during Command Interface Register(CIR) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Q8 - Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled Q15/A -1 CE INPUT/OUTPUT INPUT Selects between high-byte data INPUT/OUTPUT(BYTE/VPP = HIGH) and LSB ADDRESS(BYTE/VPP = LOW) for read operation. CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers, decoders and sense amplifiers. With CE high, the device is de-selected and power consumption reduces to Standby level upon completion of any current program or erase operations. CE must be low to select the device. Device selection occurs with the latter falling edge of CE. The first rising edge of CE disables the device. OE BYTE/VPP INPUT INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during a read cycle OE is active low. BYTE ENABLE: While operating read mode, BYTE/VPP Low places device in x8 mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/A1 selects between the high and low byte. While operating read mode, BYTE/VPP high places the device in x16 mode, and turns off the Q15/A-1 input buffer. Address A0, then becomes the lowest order address. Write Enable is active while apply 10V on the BYTE/VPP pin. VCC GND DEVICE POWER SUPPLY(5V10%) GROUND
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BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Table2.1 Bus Operations
Mode
Read Output Disable Standby Manufacturer ID Device ID MX29F1615 Write
Notes
1,5 1 1 2,4 2,4
CE
VIL VIL VIH VIL VIL
OE
VIL VIH X VIL VIL
BYTE/VPP
VIH/VIL VIH/VIL X VIH/VIL VIH/VIL
A0
X X X VIL VIH
A1
X X X VIL VIL
A9
X X X VID VID
Q0-Q7
DOUT High Z X C2H 6BH
Q8-Q14
HighZ/DOUT HIghZ X High Z/00H High Z/00H
Q15/A-1
VIL/VIH/DOUT High Z/X X VIL/OB VIL/OB
1,3,6
VIL
VIH
VHH
X
X
X
DIN
DIN
DIN
NOTES :
1. X can be VIH or VIL for address or control pins. 2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. 3. Commands for different Erase operations or Data program operations can only be successfully completed through proper command sequence. 4. VID = 11.5V- 12.5V. 5. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out. 6.VHH=9.5V~10.5V
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WRITE OPERATIONS
Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID, Erase and Program command. In the event of a read command, the CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been requested. During a program cycle, the write state machine will control the program sequences and the CIR will only respond to status reads. During a sector/chip erase cycle, the CIR will respond to status reads and erase suspend. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode until the microprocessor issues another valid command sequence. Device operations are selected by writing commands into the CIR. Table 3 below defines 16 Mbit flash command.
TABLE 3. COMMAND DEFINITIONS(Word-Wide Mode, BYTE/VPP=VHH)
Command Sequence Bus Write Cycles Req'd First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 5555H AAH 2AAAH 55H 5555H F0H RA RD 5555H AAH 2AAAH 55H 5555H 90H 00H/01H C2H/6BH 5555H AAH 2AAAH 55H 5555H A0H PA PD 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 5555H AAH 2AAAH 55H 5555H 70H X SRD 5555H AAH 2AAAH 55H 5555H 50H Read/ Reset 4 Silicon ID Read 4 Page Program 4 Chip Erase 6 Read 4 Clear 3 Status Reg. Status Reg.
Notes: 1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA). 5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14. 2. Bus operations are defined in Table 2. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the CE pulse. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of CE. SRD = Data read from status register. 5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.
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DEVICE OPERATION SILICON ID READ
The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0 and A1. The manufacturer and device codes may also be read via the command register, for instances when the MX29F1615 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 3. Byte 0 (A0=VIL) represents the manfacturer's code (MXIC=C2H) and byte 1 (A0=VIH) the device identifier code (MX29F1615=6BH).
The Silicon ID Read mode will be terminated after the following write command cycle.
Table 4. MX29F1615 Silion ID Codes
Type Manufacturer Code MX29F1615 Device Code A19 X X A18 X X A17 A16 X X X X A1 VIL A0 VIL Code(HEX) Q7 C2H* 6BH 1 0 Q6 1 1 Q5 0 1 Q4 0 0 Q3 0 1 Q2 0 0 Q1 1 1 Q0 0 1
VIL VIH
* MX29F1615 Manufacturer Code = C2H, Device Code = 6BH when BYTE/VPP = VIL MX29F1615 Manufacturer Code = 00C2H, Device Code = 006BH when BYTE/VPP= VIH
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READ/RESET COMMAND
The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX29F1615 is accessed like an EPROM. When CE and OE are low and BYTE/VPP is high or low the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. Note that the read/reset command is not valid when program or erase is in progress.
PROGRAM
Any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. The device is programmed on a page basis. If a word of data within a page is to be changed, data for the entire page can be loaded into the device. Any word that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the words of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data word has been loaded into the device, successive words are entered in the same manner. The time between word loads must be less than 30us otherwise the load period could be teminated. A6 to A19 specify the page address, i.e., the device is page-aligned on 64 words boundary. The page address must be valid during each high to low transition of CE. A0 to A5 specify the byte address within the page. The word may be loaded in any order; sequential loading is not required. If a high to low transition of CE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on Q7 is '1' at which time the device stays at read status register mode until the CIR contents are altered by a valid command sequence.
PAGE PROGRAM
To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock" write cycles. These are followed by writing the page program commandA0H. Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device. After three-cycle command sequence is given, a word load is performed by applying a low pulse on the CE input with CE low (respectively) and OE high. The address is latched on the falling edge of CE, whichever occurs last. The data is latched by the first rising edge of CE. Maximum of 64 words of data may be loaded into each page by the same procedure as outlined in the page program section below.
CHIP ERASE
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followed by the chip erase command-10H. Chip erase does not require the user to program the device prior to erase. The automatic erase begins on the rising edge of the last CE pulse in the command sequence and terminates when the status on Q7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.
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READ STATUS REGISTER
The MXIC's16 Mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status command to the CIR. After writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the CIR. A Read Array command must be written to the CIR to return to the Read Array mode. The status register bits are output on Q2 - Q7(table 6) whether the device is in the byte-wide (x8) or word-wide (x16) mode for the MX29F1615. In the word-wide mode the upper byte, Q(8:15) is set to 00H during a Read Status command. In the byte-wide mode, Q(8:14) are tri-stated and Q15/A-1 retains the low order address function. Q0Q1 is set to 0H in either x8 or x16 mode. It should be noted that the contents of the status register are latched on the falling edge of OE or CE whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE or OE must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. The Status Register is the interface between the microprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. If Erase fail or Program fail status bit is detected, the Status Register is not cleared until the Clear Status Register command is written. The MX29F1615 automatically outputs Status Register data when read after Chip Erase, Page Program or Read Status Command write cycle. The internal state machine is set for reading array data upon device power-up, or after deep power-down mode.
CLEAR STATUS REGISTER
The Eraes fail status bit (Q5) and Program fail status bit (Q4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). The status register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. The program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. To clear the status register, the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID.
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TABLE 5. MX29F1615 STATUS REGISTER
STATUS IN PROGRESS PROGRAM ERASE COMPLETE PROGRAM ERASE FAIL PROGRAM ERASE AFTER CLEARING STATUS REGISTER NOTES 1, 2 1, 3 1, 2 1, 3 1, 4 1, 4 Q7 0 0 1 1 1 1 1 Q6 0 0 0 0 0 0 0 Q5 0 0 0 0 0 1 0 Q4 0 0 0 0 1 0 0 Q3 0 0 0 0 0 0 0
NOTES: 1. Q7 : WRITE STATE MACHINE STATUS 1 = READY, 0 = BUSY Q6 : RESERVED FOR FUTURE ENHANCEMENTS Q5 : ERASE FAIL STATUS 1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE Q4 : PROGRAM FAIL STATUS 1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM Q3=0 = RESERVED FOR FUTURE ENHANCEMENTS. Other bits are reserved for future use ; mask them out when polling the Status Register. 2. PROGRAM STATUS is for the status during Page Programming. 3. ERASE STATUS is for the status during Chip Erase. 4. FAIL STATUS bit(Q4 or Q5) is provided during Page Program or Chip Erase modes respectively. 5. Q3 = 0 all the time.
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DATA PROTECTION
The MX29F1615 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE = VIH or BYTE/VPP=VIH/VIL To initiate a write cycle CE must be a logical zero, BYTE/VPP must be at VHH while OE is a logical one.
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Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART
START
BYTE/VPP=VHH
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data A0H Address 5555H
Write Program Data/Address
Loading End?
NO
YES Wait 100us
BYTE/VPP=VIH/VIL
Read Status Register
NO SR7 = 1 ? YES
SR4 = 0 ? YES
NO
Page Program Completed
Program Error
YES
Program another page?
To Continue Other Operations, Do Clear S.R. Mode First
NO
Operation Done, Device Stays At Read S.R. Mode
Note : S.R. Stands for Status Register
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Figure 2. AUTOMATIC CHIP ERASE FLOW CHART
START
BYTE/VPP=VHH
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 80H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 10H Address 5555H
BYTE/VPP=VIH/VIL
Read Status Register
NO SR7 = 1 ? YES
SR5 = 0 ? YES
NO
Chip Erase Completed
Erase Error
Operation Done, Device Stays at Read S.R. Mode
To Continue Other Operations, Do Clear S.R. Mode First
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 BYTE/VPP VALUE 0 to 70C C -65 to 125 C C -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V -0.5V to 10.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
CAPACITANCE TA = 25 f = 1.0 MHz C,
SYMBOL CIN1 CIN2 COUT PARAMETER Input Capacitance Control Pin Input Capacitance Output Capacitance MIN. TYP. MAX. 14 16 16 UNIT pF pF pF CONDITIONS VIN = 0V VIN=0V VOUT = 0V
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.6K ohm +5V
CL 1.2K ohm
DIODES = IN3064 OR EQUIVALENT
CL = 100 pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V TEST POINTS 0.8V
0.45V
2.0V 0.8V OUTPUT
INPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 10ns.
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DC CHARACTERISTICS = 0C to 70 VCC = 5V10% C,
SYMBOL IIL PARAMETER Input Load Current Output Leakage Current VCC Standby Current(CMOS) VCC Standby Current(TTL) VCC Read Current 1 NOTES MIN. 1 TYP. MAX. 10 UNITS uA TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CE= VCC 0.2V VCC = VCC Max CE= VIH VCC = VCC Max CMOS: CE = GND 0.2V BYTE/VPP=GND 0.2VorVCC 0.2V Inputs = GND 0.2V or VCC 0.2V TTL : CE = VIL, BYTE/VPP = VIL or VIH Inputs = VIL or VIH, f = 10MHz, IOUT = 0 mA VCC = VCC Max, CMOS: CE = GND 0.2V BYTE/VPP = VCC 0.2V or GND 0.2V Inputs = GND 0.2V or VCC 0.2V TTL: CE = VIL, BYTE/VPP= VIH or VIL Inputs = VIL or VIH, f = 5MHz, IOUT = 0mA CE= VIH BLock Erase Suspended Program in Progress
ILO
1
10
uA
ISB1
1
1
100
uA
ISB2
2
4
mA
ICC1
50
60
mA
ICC2
VCC Read Current
1
30
35
mA
ICC3
VCC Erase Suspend Current VCC Program Current VCC Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
1,2
5
10
mA
ICC4
1
30
50
mA
ICC5 VIL VIH VOL VOH
1 3 4 -0.3 2.4
30
50 0.8
mA V
Erase in Progress
VCC+0.3V 0.45 V V IOL = 2.1mA IOH = -2mA
2.4
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DC CHARACTERISTICS = 0C to 70 VCC = 5V10%(CONTINUE P.15) C,
NOTES: C. 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25 These currents are valid for all product versions (package and speeds). 2. ICC3 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICC3 and ICC1/2. 3. VIL min. = -1.0V for pulse width is equal to or less than 50ns. VIL min. = -2.0V for pulse width is equal to or less than 20ns. 4. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed.
AC CHARACTERISTICS READ OPERATIONS
SYMBOL tACC tCE tOE tDF tOH DESCRIPTIONS Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Delay Address to Output hold 0 0 29F1615-90 MIN. MAX. 90 90 50 35 0 0 29F1615-10 MIN. MAX. 100 100 50 35 0 0 29F1615-12 MIN. MAX. 120 120 60 35 UNIT CONDITIONS ns ns ns ns ns CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL
TEST CONDITIONS: * Input pulse levels: 0.45V/2.4V * Input rise and fall times: 10ns * Output load: 1TTL gate+100pF(Including scope and jig) * Reference levels for measuring timing: 0.8V, 2.0V
NOTE:
1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
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Figure 3. READ TIMING WAVEFORMS
Vcc Power-up
VIH
Standby
Device and address selection
Outputs Enabled Data valid
Standby
Vcc Power-down
ADDRESSES
VIL
ADDRESSES STABLE
VIH VIL
CE
VIH VIL tDF VIH
OE BYTE/VPP(1)
VIL tOE tCE tOH VOH
DATA OUT
VOL
HIGH Z
Data out valid
HIGH Z
tACC
5.0V
VCC
GND
NOTE: 1.For real world application, BYTE/VPP pin should be either static high(word mode read) or static low(byte mode read); dynamic switching of BYTE/VPP pin is not recommended.
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AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE/VPP)
Speed Options Symbol tELFL/tELFH tFLQZ tFHQV Description CE to BYTE/VPP Switching Low or High MAX BYTE/VPP Switching Low to Output HIHG ZMax BYTE/VPP Switching High to Output ActiveMin 90 5 30 90 100 5 30 100 120 5 30 120 unit ns ns ns
Figure 4. BYTE/VPP TIMING WAVEFORMS
CE
OE
BYTE/VPP
VIH VIL tELFL
BYTE/VPP Switching from word to byte mode read
Q0~Q14
Data Output (Q0~Q14)
Data Output (Q0~Q7)
Q15/A-1
tFLQZ tELFL
Q15 Output
Address Input
VIH
BYTE/VPP BYTE/VPP Switching from byte to word mode read
VIL
Q0~Q14
Data Output (Q0~Q7)
Data Output (Q0~Q14)
Q15/A-1
Address Input
Q15 Output
tFHQV
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MX29F1615
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS
SYMBOL tWC tAS tAH tDS tDH tOES tCES tGHWL tCS tCH tWP tWPH tBALC tBAL tSRA tCESR tVCS tVPS tVPH DESCRIPTION Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time CE Setup Time Read Recover Time Before Write CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Word Address Load Cycle Word Address Load Time Status Register Access Time CE Setup before S.R. Read VCC Setup Time VPP Setup Time VPP Hold Time 29F1615-90 MIN. MAX. 90 0 50 50 0 0 0 0 0 0 50 30 0.3 100 70 70 50 2 2 30 29F1615-10 MIN. MAX. 100 0 50 50 0 0 0 0 0 0 50 30 0.3 100 70 70 50 2 2 30 29F1615-12 MIN. MAX. 120 0 60 60 0 0 0 0 0 0 60 50 0.3 100 90 70 50 2 2 30 ns ns ns ns us us ns ns us us us UNIT ns ns ns ns ns ns ns
P/N: PM0615
19
REV. 1.1, JUN. 15, 2001
MX29F1615
Figure 5. COMMAND WRITE TIMING WAVEFORMS
CE
tOES
OE
tVPS 10V tVPH
BYTE/VPP
tAS
tAH
ADDRESSES
VALID
tDH HIGH Z
DATA
tDS
DIN
VCC
tVCS
P/N: PM0615
20
REV. 1.1, JUN. 15, 2001
MX29F1615
Figure 6. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS
A0~A5
55H
AAH
55H
Word offset Address
Last Word offset Address
A6~A14
tAS
55H
tAH
2AH
55H
Page Address
A15~A19
Page Address
tWC
tBALC
tBAL
CE
tWP tVPS
tWPH
tVPH
BYTE/VPP
10V
tCES
OE
tDS tDH
tSRA
DATA
AAH
55H
A0H
Write Data
Last Write Data
SRD
NOTE: 1.Please refer to page 9 for detail page program operation.
P/N: PM0615
21
REV. 1.1, JUN. 15, 2001
MX29F1615
Figure 7. AUTOMATIC CHIP ERASE TIMING WAVEFORMS
A0~A19
5555H
tAS tAH
2AAAH
5555H
5555H
2AAAH
5555H
tCESR
CE
tWP tVPS tWPH
tVPH
BYTE/VPP
VHH 10V VIH/VIL
tWC
tCES
OE
tDS tDH
tSRA
DATA
AAH
55H
80H
AAH
55H
10H
SRD
P/N: PM0615
22
REV. 1.1, JUN. 15, 2001
MX29F1615
ERASE AND PROGRAMMING PERFORMANCE(1)
PARAMETER
Chip Erase Time Page Programming Time Chip Programming Time Erase/Program Cycles Word Program Time 100 14 420
MIN.
LIMITS TYP.(2)
32 0.9 14
MAX.
256 27 42
UNITS
sec ms sec Cycles us
Note:
1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25 C,5V.
LATCHUP CHARACTERISTICS
MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 13.5V Vcc + 1.0V +100mA
P/N: PM0615
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REV. 1.1, JUN. 15, 2001
MX29F1615
PACKAGE INFORMATION
42-PIN PLASTIC DIP(600 mil)
P/N: PM0615
24
REV. 1.1, JUN. 15, 2001
MX29F1615
REVISION HISTORY
Revision 1.1 Description To modify "Package Information" Page P24 Date JUN/15/2001
P/N: PM0615
25
REV. 1.1, JUN. 15, 2001
MX29F1615
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100 FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385 FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300 FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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